A traditional inverter circuit or NOT gate is constructed from two complementary switches connected in series and configured such that the switches are alternatively enabled. Metal-oxide-semiconductor field-effect transistors (MOSFET) are currently widely used in the fabrication of inverter circuits or NOT gates because their high input impedance results in low power dissipation after the MOSFETs are driven to enabled and disabled states, their low output impedance results in fast switching speeds for sharp edges, and their small size relative to bipolar junction transistors (BJT) provides for a high level of packing density. Complementary MOSFET (CMOS) inverters are typically fabricated with a p-well region formed in an n-substrate with an n-channel MOSFET fabricated in the p-well region and a p-channel MOSFET fabricated in the n-substrate, alternatively a CMOS inverter can be fabricated with a n-well region formed in a p-substrate with the n-channel MOSFET fabricated in the p-substrate and the p-channel MOSFET fabricated in an n-well.
FIG. 1A illustrates the basic structure for a CMOS inverter 100 having an n-channel MOSFET 102 fabricated in a p-well region 106 in an n-substrate 108 and a p-channel MOSFET 104 fabricated in the n-substrate 108. The n-channel MOSFET 102 is constructed by depositing an n-region 110 in the p-well region 106 and a conductor 112 above the n-region 110 to form a drain terminal, depositing a separate n-region 114 in the p-well region 106 and a conductor 116 above the n-region 114 to form source terminal, and depositing an insulating layer 118 of dielectric material on the p-well region separating the two separate n-regions, called the channel region, and a conductor 120 above the insulating layer 118 to form a gate terminal. The p-channel MOSFET 104 is constructed by depositing a p-region 122 in the n-substrate 108 and a conductor 124 above the p-region 122 to form a drain terminal, depositing a separate p-region 126 in the n-substrate and a conductor 128 above the p-region 126 to form a drain terminal, and depositing an insulating layer of dielectric material 130 on the n-substrate region separating the two separate p-regions, called the channel region, and a conductor 132 above the insulating layer 130 to form a gate terminal. The gate terminal conductor 120 of the n-channel MOSFET 102 and the gate terminal conductor 132 of the p-channel MOSFET are connected to each other to form an input 136 for the CMOS inverter. The drain terminal conductor 116 of the n-channel MOSFET and the drain terminal conductor 124 of the p-channel MOSFET are connected to each other to form an output 134 for the CMOS inverter. The source terminal conductor 112 of the n-channel MOSFET and the p-well 106 are connected to ground to minimize the voltage differential between the source terminal and the p-well to reduce the change in threshold voltage of the n-channel MOSFET caused the body effect. The source terminal conductor 128 of the p-channel MOSFET and the n-substrate 108 are connected to a voltage source Vdd to minimize the voltage differential between the source terminal and the n-substrate to reduce change in threshold voltage of the p-channel MOSFET caused by the body effect. The body effect can negatively impact the performance of the CMOS inverter by changing the threshold voltages of the n-channel MOSFET and the p-channel MOSFET.
FIG. 1A further illustrates the CMOS inverter in operation converting a positive voltage input signal to a ground voltage output signal. The positive voltage input signal is applied to the CMOS inverter input 136 and the positive voltage input signal charges both the gate terminal conductor 120 for n-channel MOSFET 102 and the gate terminal conductor 132 for the p-channel MOSFET 104 to the voltage level of the positive voltage input signal. The gate terminal conductors 120, 132, insulating layers 118, 130, and channel regions of both the n-channel MOSFET 102 and the p-channel MOSFET 104 form structures similar to parallel plate capacitors. Charging the gate terminal conductor 120 of the n-channel MOSFET 102 to a positive voltage level with respect to the p-well 106 induces a uniform electric field between the gate terminal conductor 120 and the channel region of the p-well 106 for relatively long channel regions and a somewhat non-uniform electric field will be induced for short channel regions. When the positive voltage level has sufficient amplitude to induce an electric field that penetrates the channel region of p-well 106, the electric field pushes the holes in the p-well 106 away from the channel region and pulls the electrons in p-well 106 toward the channel region forming an electron inversion layer 138 in the channel region of the p-well 106. The electron inversion layer 138 connects n-region 110 formed as part of the source terminal with the n-region 114 formed as part of the drain terminal and allows current to flow between the source terminal and the drain terminal. Charging the gate terminal conductor 132 of the p-channel MOSFET to the positive voltage level with respect to the n-substrate induces a uniform electric field between the gate terminal conductor 132 and the channel region of the n-substrate 108 for relatively long channel regions and a somewhat non-uniform electric field will be induced for short channel regions. When the positive voltage level has sufficient amplitude to induce an electric field that penetrates the channel region of n-substrate 108, the electric field pulls electrons in the n-substrate toward the channel region forming an electron accumulation layer, not shown in FIG. 1A. The electron accumulation layer limits current from flowing between the p-region 126 formed as part of the source terminal and p-region 122 formed as part of the drain terminal.
FIG. 1B illustrates the basic structure for a CMOS inverter 150 having an n-channel MOSFET 152 fabricated in a p-substrate 158 and p-channel MOSFET 154 fabricated in an n-well 156 in the p-substrate 158. The n-channel MOSFET 152 is constructed by depositing an n-region 160 in the p-substrate 158 and a conductor 162 above the n-region 160 to form a drain terminal, depositing a separate n-region 164 in the p-substrate 158 and a conductor 166 above the n-region 164 to form source terminal, and depositing an insulating layer 168 of dielectric material on the p-substrate region separating the two separate n-regions, called the channel region, and a conductor 170 above the insulating layer 168 to form a gate terminal. The p-channel MOSFET 154 is constructed by depositing a p-region 172 in the n-well 156 and a conductor 174 above the p-region 172 to form a drain terminal, depositing a separate p-region 176 in the n-well and a conductor 178 above the p-region 176 to form a drain terminal, and depositing an insulating layer 180 of dielectric material on the n-well region separating the two separate p-regions, called the channel region, and a conductor 182 above the insulating layer 180 to form a gate terminal. The gate terminal conductor 170 of the n-channel MOSFET 152 and the gate terminal conductor 182 of the p-channel MOSFET are connected to each other to form an input 186 for the CMOS inverter. The drain terminal conductor 166 of the n-channel MOSFET and the drain terminal conductor 174 of the p-channel MOSFET are connected to each other to form an output 184 for the CMOS inverter. The source terminal conductor 162 of the n-channel MOSFET and the p-substrate 158 are connected to ground to minimize the voltage differential between the source terminal and the p-substrate to reduce the change in threshold voltage of the n-channel MOSFET caused the body effect. The source terminal conductor 178 of the p-channel MOSFET and the n-well 156 are connected to a voltage source Vdd to minimize the voltage differential between the source terminal and the n-well to the reduce change in threshold voltage of the p-channel MOSFET caused by the body effect. The body effect can negatively impact the performance of the CMOS inverter by changing the threshold voltages of the n-channel MOSFET and the p-channel MOSFET.
FIG. 1B further illustrates the CMOS inverter in operation converting a negative voltage input signal to a Vdd voltage output signal. The negative voltage input signal is applied to the CMOS inverter input 186 and the negative voltage input signal charges both the gate terminal conductor 170 for n-channel MOSFET 152 and the gate terminal conductor 182 for the p-channel MOSFET 154 to the negative voltage level of the negative voltage input signal. The gate terminal conductors 170, 182, insulating layers 168, 180, and channel regions of both the n-channel MOSFET 152 and the p-channel MOSFET 154 form structures similar to parallel plate capacitors. Charging the gate terminal conductor 170 of the n-channel MOSFET 152 to a negative voltage level with respect to the p-substrate 158 induces a uniform electric field between the gate terminal conductor 170 and the channel region of the p-substrate 158 for relatively long channel regions and a somewhat non-uniform electric field will be induced for short channel regions. When the negative voltage level has sufficient amplitude to induce an electric field that penetrates the channel region of p-substrate 158, the electric field pulls holes in the p-substrate toward the channel region forming a hole accumulation layer, not shown in FIG. 1B. The hole accumulation layer limits current from flowing between the n-region 164 formed as part of the drain terminal and n-region 160 formed as part of the source terminal. Charging the gate terminal conductor 182 of the p-channel MOSFET to the negative voltage level with respect to the n-well induces a uniform electric field between the gate terminal conductor 182 and the channel region of the n-well 156 for relatively long channel regions and a somewhat non-uniform electric field will be induced for short channel regions. When the negative voltage level has sufficient amplitude to induce an electric field that penetrates the channel region of n-well 156, the electric field pushes the electrons in the n-well 156 away from the channel region and pulls the holes in n-well 156 toward the channel region forming a hole inversion layer 188 in the channel region of the n-well 156. The hole inversion layer 188 connects p-region 176 formed as part of the source terminal with the p-region 172 formed as part of the drain terminal and allows current to flow between the source terminal and the drain terminal.
The coplanar layout of the complementary MOSFETs coupled with the increasingly difficult scaling of MOSFETs to smaller sizes creates a barrier to reducing the amount of chip area consumed by the inverter circuits or NOT gates. MOSFETs at the 90 nm technology node have high leakage currents resulting in high standby power dissipation at short channel lengths due to well-known problems associated with scaling FET devices threshold voltages. In large measure this scaling problem is caused by the difficulty in gate control of the electrical characteristics of the FET channel region in the silicon substrate. The problem is expected to get much worse as technology dimensions shrink to 65 nm, 45 nm, and 20 nm values. There is concern that scaling below 20 nm using silicon substrates may become impractical from both technical feasibility and a fabrication cost perspectives. In addition to the problems presented by scaling FET devices to smaller sizes, the physical construction of an inverter circuit or NOT gate from MOSFETs having individually doped regions and doped well regions fabricated in a semiconductor substrate creates parasitic components that negatively impact performance of the inverter circuit or NOT gate.
U.S. Pat. No. 7,598,544 discloses carbon nanotube FETs, static random access memory fabricated using carbon nanotube FETs, and methods for making the same. U.S. Published Patent Application No. 20060183278 also discloses carbon nanotube FETs and methods for making the same.
U.S. Pat. Nos. 6,835,591, 7,335,395, 7,259,410, 6,924,538, and 7,375,369 disclose approaches for making nanotube films and articles, e.g., nanotube fabrics such as carbon nanotube fabrics and articles made therefrom, the entire contents of each of which is incorporated herein by reference.
U.S. Patent Application Publication Nos. 20080299307, 20050058797, 20080012047, 20060183278, 20080251723, 20080170429 also disclose approaches for making nanotube films and articles, e.g., nanotube fabrics such as carbon nanotube fabrics and articles made therefrom, the entire contents of each of which is incorporated herein by reference.
U.S. Pat. No. 7,115,901 discloses non-volatile field effect devices and circuits having an electromechanically-deflectable, nanotube switching element that may comprise a nanofabric, and methods for making the same. U.S. Patent Application Publication No. 20100039138 discloses field programmable device chips comprising nanotube elements, which may comprise carbon nanotube fabrics, for example, and methods for making the same. U.S. Patent Application Publication No. 20080159042 discloses non-volatile latch circuits comprising nanotube switching elements, which may comprise carbon nanotube fabrics, for example, and methods for making the same. U.S. Patent Application Publication No. 20080157126 discloses non-volatile nanotube diode devices comprising nanotube switching elements, which may comprise carbon nanotube fabrics, for example, and methods for making the same. U.S. Patent Application Publication No. 20100001267 discloses nanotube memory arrays comprising memory cells having nanotube fabric layers and methods for making the same. The entire contents of U.S. Patent Application Publication Nos. 20100039138, 20080159042, 20080157126, and 20100001267 and U.S. Pat. No. 7,115,901 are incorporated herein by reference.